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ADE7880
The recommended procedure to manage SAG events is the
IPPHASE/VPPHASE BITS
Data Sheet
following:
31
27 26 25 24 23
0
1.
Enable SAG interrupts in the MASK1 register by setting
Bit 16 (SAG) to 1.
00000
PEAK DETECTED
ON PHASE C
24-BIT UNSIGNED NUMBER
PEAK DETECTED
ON PHASE A
2.
3.
4.
5.
When a SAG event happens, the IRQ1 interrupt pin goes
low and Bit 16 (SAG) in the STATUS1 is set to 1.
The STATUS1 register is read with Bit 16 (SAG) set to 1.
The PHSTATUS register is read, identifying on which
phase or phases a SAG event happened.
The STATUS1 register is written with Bit 16 (SAG) set to 1.
Immediately, the SAG bit is erased.
PEAK DETECTED
ON PHASE B
Figure 58. Composition of IPEAK[31:0] and VPEAK[31:0] Registers
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF FIRST
PEAKCYC PERIOD
END OF FIRST
PEAKCYC = 16 PERIOD
SAG Level Set
The content of the SAGLVL[23:0] SAG level register is compared
to the absolute value of the output from HPF. Writing 5,928,256
(0x5A7540) to the SAGLVL register, puts the SAG detection
level at full scale (see the Voltage Channel ADC section), thus;
PHASE A
CURRENT
END OF SECOND
PEAKCYC = 16 PERIOD
the SAG event is triggered continuously. Writing 0x00 or 0x01
puts the SAG detection level at 0, therefore, the SAG event is
never triggered.
BIT 24
OF IPEAK
BIT 24 OF IPEAK
CLEARED TO 0 AT
THE END OF SECOND
PEAKCYC PERIOD
31
0000 0000
24 23
24-BIT NUMBER
0
Figure 57. SAGLVL Register Transmitted as a 32-Bit Word
As stated in the Current Waveform Gain Registers section, the
serial ports of the ADE7880 work on 32-, 16-, or 8-bit words.
PHASE B
CURRENT
The SAGLVL register is accessed as a 32-bit register with eight
MSBs padded with 0s. See Figure 57 for details.
Peak Detection
BIT 25
OF IPEAK
PEAK VALUE WRITTEN INTO
IPEAK AT THE END OF
SECOND PEAKCYC PERIOD
Figure 59. Peak Level Detection
BIT 25 OF IPEAK
SET TO 1 AT THE
END OF SECOND
PEAKCYC PERIOD
The ADE7880 records the maximum absolute values reached by
the voltage and current channels over a certain number of half-
line cycles and stores them into the less significant 24 bits of the
VPEAK and IPEAK 32-bit registers.
The PEAKCYC register contains the number of half-line cycles
used as a time base for the measurement. The circuit uses the
zero-crossing points identified by the zero-crossing detection
circuit. Bits[4:2] (PEAKSEL[2:0]) in the MMODE register select
the phases upon which the peak measurement is performed. Bit 2
selects Phase A, Bit 3 selects Phase B, and Bit 4 selects Phase C.
Selecting more than one phase to monitor the peak values
decreases proportionally the measurement period indicated in
the PEAKCYC register because zero crossings from more
phases are involved in the process. When a new peak value is
determined, one of Bits[26:24] (IPPHASE[2:0] or VPPHASE[2:0])
in the IPEAK and VPEAK registers is set to 1, identifying the
phase that triggered the peak detection event. For example, if a
peak value has been identified on Phase A current, Bit 24
(IPPHASE[0]) in the IPEAK register is set to 1. If next time a
new peak value is measured on Phase B, Bit 24 (IPPHASE[0])
of the IPEAK register is cleared to 0, and Bit 25 (IPPHASE[1])
of the IPEAK register is set to 1. Figure 58 shows the
composition of the IPEAK and VPEAK registers.
current channel when measurements on Phase A and Phase B are
enabled (Bit PEAKSEL[2:0] in the MMODE register are 011).
PEAKCYC is set to 16, meaning that the peak measurement
cycle is four line periods. The maximum absolute value of Phase A
is the greatest during the first four line periods (PEAKCYC = 16),
so the maximum absolute value is written into the less signifi-
cant 24 bits of the IPEAK register, and Bit 24 (IPPHASE[0]) of
the IPEAK register is set to 1 at the end of the period. This bit
remains at 1 for the duration of the second PEAKCYC period of
four line cycles. The maximum absolute value of Phase B is the
greatest during the second PEAKCYC period; therefore, the
maximum absolute value is written into the less significant
24 bits of the IPEAK register, and Bit 25 (IPPHASE[1]) in the
IPEAK register is set to 1 at the end of the period.
At the end of the peak detection period in the current channel,
Bit 23 (PKI) in the STATUS1 register is set to 1. If Bit 23 (PKI)
in the MASK1 register is set, the IRQ1 interrupt pin is driven low
at the end of the PEAKCYC period, and Status Bit 23 (PKI) in
the STATUS1 register is set to 1. In a similar way, at the end of
the peak detection period in the voltage channel, Bit 24 (PKV) in
the STATUS1 register is set to 1. If Bit 24 (PKV) in the MASK1
register is set, the IRQ1 interrupt pin is driven low at the end of
PEAKCYC period and Status Bit 24 (PKV) in the STATUS1
Rev. A | Page 34 of 104
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